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https://gitlab.com/suyu-emu/suyu.git
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404 lines
16 KiB
C++
404 lines
16 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cmath>
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#include <unordered_map>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::IpaMode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset, const std::size_t size)
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: program_code{program_code}, main_offset{main_offset}, program_size{size} {
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Decode();
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}
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ShaderIR::~ShaderIR() = default;
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Node ShaderIR::GetRegister(Register reg) {
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if (reg != Register::ZeroIndex) {
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used_registers.insert(static_cast<u32>(reg));
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}
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return MakeNode<GprNode>(reg);
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}
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Node ShaderIR::GetImmediate19(Instruction instr) {
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return Immediate(instr.alu.GetImm20_19());
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}
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Node ShaderIR::GetImmediate32(Instruction instr) {
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return Immediate(instr.alu.GetImm20_32());
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}
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Node ShaderIR::GetConstBuffer(u64 index_, u64 offset_) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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const auto [entry, is_new] = used_cbufs.try_emplace(index);
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entry->second.MarkAsUsed(offset);
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return MakeNode<CbufNode>(index, Immediate(offset));
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}
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Node ShaderIR::GetConstBufferIndirect(u64 index_, u64 offset_, Node node) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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const auto [entry, is_new] = used_cbufs.try_emplace(index);
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entry->second.MarkAsUsedIndirect();
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const Node final_offset = [&]() {
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// Attempt to inline constant buffer without a variable offset. This is done to allow
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// tracking LDC calls.
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if (const auto gpr = std::get_if<GprNode>(&*node)) {
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if (gpr->GetIndex() == Register::ZeroIndex) {
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return Immediate(offset);
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}
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}
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return Operation(OperationCode::UAdd, NO_PRECISE, node, Immediate(offset));
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}();
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return MakeNode<CbufNode>(index, final_offset);
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}
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Node ShaderIR::GetPredicate(u64 pred_, bool negated) {
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const auto pred = static_cast<Pred>(pred_);
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if (pred != Pred::UnusedIndex && pred != Pred::NeverExecute) {
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used_predicates.insert(pred);
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}
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return MakeNode<PredicateNode>(pred, negated);
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}
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Node ShaderIR::GetPredicate(bool immediate) {
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return GetPredicate(static_cast<u64>(immediate ? Pred::UnusedIndex : Pred::NeverExecute));
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}
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Node ShaderIR::GetInputAttribute(Attribute::Index index, u64 element, Node buffer) {
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used_input_attributes.emplace(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), buffer);
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}
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Node ShaderIR::GetPhysicalInputAttribute(Tegra::Shader::Register physical_address, Node buffer) {
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uses_physical_attributes = true;
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return MakeNode<AbufNode>(GetRegister(physical_address), buffer);
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}
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Node ShaderIR::GetOutputAttribute(Attribute::Index index, u64 element, Node buffer) {
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if (index == Attribute::Index::LayerViewportPointSize) {
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switch (element) {
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case 0:
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UNIMPLEMENTED();
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break;
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case 1:
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uses_layer = true;
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break;
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case 2:
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uses_viewport_index = true;
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break;
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case 3:
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uses_point_size = true;
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break;
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}
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}
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if (index == Attribute::Index::ClipDistances0123 ||
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index == Attribute::Index::ClipDistances4567) {
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const auto clip_index =
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static_cast<u32>((index == Attribute::Index::ClipDistances4567 ? 1 : 0) + element);
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used_clip_distances.at(clip_index) = true;
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}
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used_output_attributes.insert(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), buffer);
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}
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Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) {
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const Node node = MakeNode<InternalFlagNode>(flag);
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if (negated) {
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return Operation(OperationCode::LogicalNegate, node);
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}
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return node;
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}
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Node ShaderIR::GetLocalMemory(Node address) {
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return MakeNode<LmemNode>(address);
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}
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Node ShaderIR::GetTemporal(u32 id) {
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return GetRegister(Register::ZeroIndex + 1 + id);
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}
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Node ShaderIR::GetOperandAbsNegFloat(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::FAbsolute, NO_PRECISE, value);
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}
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if (negate) {
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value = Operation(OperationCode::FNegate, NO_PRECISE, value);
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}
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return value;
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}
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Node ShaderIR::GetSaturatedFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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const Node positive_zero = Immediate(std::copysignf(0, 1));
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const Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::FClamp, NO_PRECISE, value, positive_zero, positive_one);
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}
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Node ShaderIR::ConvertIntegerSize(Node value, Tegra::Shader::Register::Size size, bool is_signed) {
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switch (size) {
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case Register::Size::Byte:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(24));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(24));
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return value;
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case Register::Size::Short:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(16));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(16));
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case Register::Size::Word:
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// Default - do nothing
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return value;
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default:
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UNREACHABLE_MSG("Unimplemented conversion size: {}", static_cast<u32>(size));
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return value;
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}
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}
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Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed) {
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if (!is_signed) {
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// Absolute or negate on an unsigned is pointless
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return value;
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}
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if (absolute) {
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value = Operation(OperationCode::IAbsolute, NO_PRECISE, value);
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}
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if (negate) {
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value = Operation(OperationCode::INegate, NO_PRECISE, value);
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}
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return value;
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}
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Node ShaderIR::UnpackHalfImmediate(Instruction instr, bool has_negation) {
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const Node value = Immediate(instr.half_imm.PackImmediates());
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if (!has_negation) {
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return value;
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}
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const Node first_negate = GetPredicate(instr.half_imm.first_negate != 0);
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const Node second_negate = GetPredicate(instr.half_imm.second_negate != 0);
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return Operation(OperationCode::HNegate, NO_PRECISE, value, first_negate, second_negate);
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}
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Node ShaderIR::UnpackHalfFloat(Node value, Tegra::Shader::HalfType type) {
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return Operation(OperationCode::HUnpack, type, value);
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}
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Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
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switch (merge) {
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case Tegra::Shader::HalfMerge::H0_H1:
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return src;
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case Tegra::Shader::HalfMerge::F32:
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return Operation(OperationCode::HMergeF32, src);
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case Tegra::Shader::HalfMerge::Mrg_H0:
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return Operation(OperationCode::HMergeH0, dest, src);
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case Tegra::Shader::HalfMerge::Mrg_H1:
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return Operation(OperationCode::HMergeH1, dest, src);
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}
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UNREACHABLE();
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return src;
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}
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Node ShaderIR::GetOperandAbsNegHalf(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::HAbsolute, NO_PRECISE, value);
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}
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if (negate) {
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value = Operation(OperationCode::HNegate, NO_PRECISE, value, GetPredicate(true),
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GetPredicate(true));
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}
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return value;
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}
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Node ShaderIR::GetSaturatedHalfFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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const Node positive_zero = Immediate(std::copysignf(0, 1));
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const Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::HClamp, NO_PRECISE, value, positive_zero, positive_one);
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}
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Node ShaderIR::GetPredicateComparisonFloat(PredCondition condition, Node op_a, Node op_b) {
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const std::unordered_map<PredCondition, OperationCode> PredicateComparisonTable = {
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{PredCondition::LessThan, OperationCode::LogicalFLessThan},
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{PredCondition::Equal, OperationCode::LogicalFEqual},
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{PredCondition::LessEqual, OperationCode::LogicalFLessEqual},
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{PredCondition::GreaterThan, OperationCode::LogicalFGreaterThan},
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{PredCondition::NotEqual, OperationCode::LogicalFNotEqual},
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{PredCondition::GreaterEqual, OperationCode::LogicalFGreaterEqual},
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{PredCondition::LessThanWithNan, OperationCode::LogicalFLessThan},
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{PredCondition::NotEqualWithNan, OperationCode::LogicalFNotEqual},
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{PredCondition::LessEqualWithNan, OperationCode::LogicalFLessEqual},
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{PredCondition::GreaterThanWithNan, OperationCode::LogicalFGreaterThan},
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{PredCondition::GreaterEqualWithNan, OperationCode::LogicalFGreaterEqual}};
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const auto comparison{PredicateComparisonTable.find(condition)};
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UNIMPLEMENTED_IF_MSG(comparison == PredicateComparisonTable.end(),
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"Unknown predicate comparison operation");
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Node predicate = Operation(comparison->second, NO_PRECISE, op_a, op_b);
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if (condition == PredCondition::LessThanWithNan ||
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condition == PredCondition::NotEqualWithNan ||
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condition == PredCondition::LessEqualWithNan ||
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condition == PredCondition::GreaterThanWithNan ||
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condition == PredCondition::GreaterEqualWithNan) {
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predicate = Operation(OperationCode::LogicalOr, predicate,
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Operation(OperationCode::LogicalFIsNan, op_a));
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predicate = Operation(OperationCode::LogicalOr, predicate,
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Operation(OperationCode::LogicalFIsNan, op_b));
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}
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return predicate;
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}
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Node ShaderIR::GetPredicateComparisonInteger(PredCondition condition, bool is_signed, Node op_a,
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Node op_b) {
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const std::unordered_map<PredCondition, OperationCode> PredicateComparisonTable = {
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{PredCondition::LessThan, OperationCode::LogicalILessThan},
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{PredCondition::Equal, OperationCode::LogicalIEqual},
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{PredCondition::LessEqual, OperationCode::LogicalILessEqual},
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{PredCondition::GreaterThan, OperationCode::LogicalIGreaterThan},
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{PredCondition::NotEqual, OperationCode::LogicalINotEqual},
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{PredCondition::GreaterEqual, OperationCode::LogicalIGreaterEqual},
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{PredCondition::LessThanWithNan, OperationCode::LogicalILessThan},
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{PredCondition::NotEqualWithNan, OperationCode::LogicalINotEqual},
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{PredCondition::LessEqualWithNan, OperationCode::LogicalILessEqual},
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{PredCondition::GreaterThanWithNan, OperationCode::LogicalIGreaterThan},
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{PredCondition::GreaterEqualWithNan, OperationCode::LogicalIGreaterEqual}};
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const auto comparison{PredicateComparisonTable.find(condition)};
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UNIMPLEMENTED_IF_MSG(comparison == PredicateComparisonTable.end(),
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"Unknown predicate comparison operation");
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Node predicate = SignedOperation(comparison->second, is_signed, NO_PRECISE, op_a, op_b);
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UNIMPLEMENTED_IF_MSG(condition == PredCondition::LessThanWithNan ||
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condition == PredCondition::NotEqualWithNan ||
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condition == PredCondition::LessEqualWithNan ||
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condition == PredCondition::GreaterThanWithNan ||
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condition == PredCondition::GreaterEqualWithNan,
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"NaN comparisons for integers are not implemented");
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return predicate;
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}
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Node ShaderIR::GetPredicateComparisonHalf(Tegra::Shader::PredCondition condition, Node op_a,
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Node op_b) {
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const std::unordered_map<PredCondition, OperationCode> PredicateComparisonTable = {
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{PredCondition::LessThan, OperationCode::Logical2HLessThan},
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{PredCondition::Equal, OperationCode::Logical2HEqual},
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{PredCondition::LessEqual, OperationCode::Logical2HLessEqual},
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{PredCondition::GreaterThan, OperationCode::Logical2HGreaterThan},
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{PredCondition::NotEqual, OperationCode::Logical2HNotEqual},
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{PredCondition::GreaterEqual, OperationCode::Logical2HGreaterEqual},
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{PredCondition::LessThanWithNan, OperationCode::Logical2HLessThanWithNan},
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{PredCondition::NotEqualWithNan, OperationCode::Logical2HNotEqualWithNan},
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{PredCondition::LessEqualWithNan, OperationCode::Logical2HLessEqualWithNan},
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{PredCondition::GreaterThanWithNan, OperationCode::Logical2HGreaterThanWithNan},
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{PredCondition::GreaterEqualWithNan, OperationCode::Logical2HGreaterEqualWithNan}};
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const auto comparison{PredicateComparisonTable.find(condition)};
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UNIMPLEMENTED_IF_MSG(comparison == PredicateComparisonTable.end(),
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"Unknown predicate comparison operation");
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const Node predicate = Operation(comparison->second, NO_PRECISE, op_a, op_b);
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return predicate;
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}
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OperationCode ShaderIR::GetPredicateCombiner(PredOperation operation) {
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const std::unordered_map<PredOperation, OperationCode> PredicateOperationTable = {
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{PredOperation::And, OperationCode::LogicalAnd},
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{PredOperation::Or, OperationCode::LogicalOr},
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{PredOperation::Xor, OperationCode::LogicalXor},
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};
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const auto op = PredicateOperationTable.find(operation);
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UNIMPLEMENTED_IF_MSG(op == PredicateOperationTable.end(), "Unknown predicate operation");
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return op->second;
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}
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Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) {
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switch (cc) {
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case Tegra::Shader::ConditionCode::NEU:
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return GetInternalFlag(InternalFlag::Zero, true);
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default:
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UNIMPLEMENTED_MSG("Unimplemented condition code: {}", static_cast<u32>(cc));
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return GetPredicate(static_cast<u64>(Pred::NeverExecute));
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}
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}
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void ShaderIR::SetRegister(NodeBlock& bb, Register dest, Node src) {
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
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}
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void ShaderIR::SetPredicate(NodeBlock& bb, u64 dest, Node src) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetPredicate(dest), src));
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}
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void ShaderIR::SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetInternalFlag(flag), value));
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}
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void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
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bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
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}
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void ShaderIR::SetTemporal(NodeBlock& bb, u32 id, Node value) {
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SetRegister(bb, Register::ZeroIndex + 1 + id, value);
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}
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void ShaderIR::SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc) {
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if (!sets_cc) {
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return;
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}
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const Node zerop = Operation(OperationCode::LogicalFEqual, value, Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, zerop);
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_cc) {
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if (!sets_cc) {
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return;
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}
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const Node zerop = Operation(OperationCode::LogicalIEqual, value, Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, zerop);
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, value, Immediate(offset),
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Immediate(bits));
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}
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} // namespace VideoCommon::Shader
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