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VideoCore/Shader: Remove dynamic control flow in (Get)UniformOffset
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d27cb1dedc
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@ -161,21 +161,16 @@ struct ShaderSetup {
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std::array<Math::Vec4<u8>, 4> i;
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std::array<Math::Vec4<u8>, 4> i;
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} uniforms;
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} uniforms;
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static size_t UniformOffset(RegisterType type, unsigned index) {
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static size_t GetFloatUniformOffset(unsigned index) {
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switch (type) {
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return offsetof(ShaderSetup, uniforms.f) + index * sizeof(Math::Vec4<float24>);
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case RegisterType::FloatUniform:
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}
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return offsetof(ShaderSetup, uniforms.f) + index * sizeof(Math::Vec4<float24>);
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case RegisterType::BoolUniform:
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static size_t GetBoolUniformOffset(unsigned index) {
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return offsetof(ShaderSetup, uniforms.b) + index * sizeof(bool);
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return offsetof(ShaderSetup, uniforms.b) + index * sizeof(bool);
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}
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case RegisterType::IntUniform:
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static size_t GetIntUniformOffset(unsigned index) {
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return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
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return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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}
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> program_code;
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@ -185,7 +185,7 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
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src_ptr = SETUP;
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src_ptr = SETUP;
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src_offset = ShaderSetup::UniformOffset(RegisterType::FloatUniform, src_reg.GetIndex());
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src_offset = ShaderSetup::GetFloatUniformOffset(src_reg.GetIndex());
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} else {
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} else {
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src_ptr = STATE;
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src_ptr = STATE;
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src_offset = UnitState<false>::InputOffset(src_reg);
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src_offset = UnitState<false>::InputOffset(src_reg);
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@ -348,8 +348,7 @@ void JitShader::Compile_EvaluateCondition(Instruction instr) {
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}
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}
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void JitShader::Compile_UniformCondition(Instruction instr) {
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void JitShader::Compile_UniformCondition(Instruction instr) {
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size_t offset =
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size_t offset = ShaderSetup::GetBoolUniformOffset(instr.flow_control.bool_uniform_id);
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ShaderSetup::UniformOffset(RegisterType::BoolUniform, instr.flow_control.bool_uniform_id);
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cmp(byte[SETUP + offset], 0);
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cmp(byte[SETUP + offset], 0);
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}
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}
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@ -732,8 +731,7 @@ void JitShader::Compile_LOOP(Instruction instr) {
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// This decodes the fields from the integer uniform at index instr.flow_control.int_uniform_id.
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// This decodes the fields from the integer uniform at index instr.flow_control.int_uniform_id.
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// The Y (LOOPCOUNT_REG) and Z (LOOPINC) component are kept multiplied by 16 (Left shifted by
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// The Y (LOOPCOUNT_REG) and Z (LOOPINC) component are kept multiplied by 16 (Left shifted by
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// 4 bits) to be used as an offset into the 16-byte vector registers later
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// 4 bits) to be used as an offset into the 16-byte vector registers later
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size_t offset =
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size_t offset = ShaderSetup::GetIntUniformOffset(instr.flow_control.int_uniform_id);
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ShaderSetup::UniformOffset(RegisterType::IntUniform, instr.flow_control.int_uniform_id);
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mov(LOOPCOUNT, dword[SETUP + offset]);
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mov(LOOPCOUNT, dword[SETUP + offset]);
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mov(LOOPCOUNT_REG, LOOPCOUNT);
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mov(LOOPCOUNT_REG, LOOPCOUNT);
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shr(LOOPCOUNT_REG, 4);
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shr(LOOPCOUNT_REG, 4);
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