gitlab-com-suyu-emu/suyu
1
0
Fork 0
mirror of https://gitlab.com/suyu-emu/suyu.git synced 2024-03-15 23:15:44 +00:00
Code Issues Projects Releases Wiki Activity

Merge pull request #2921 from jroweboy/batch-fix-2

Browse source 
GPU: Add draw for immediate and batch modes
This commit is contained in:
James Rowe 2017-09-24 07:57:16 -06:00 committed by GitHub
parent a7758b0b36 19d41dcc6e
commit 93930a966f
1 changed files with 17 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
src/video_core/command_processor.cpp
View file

@ -243,6 +243,15 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
ASSERT(!g_state.geometry_pipeline.NeedIndexInput()); ASSERT(!g_state.geometry_pipeline.NeedIndexInput());
g_state.geometry_pipeline.Setup(shader_engine); g_state.geometry_pipeline.Setup(shader_engine);
g_state.geometry_pipeline.SubmitVertex(output); g_state.geometry_pipeline.SubmitVertex(output);
// TODO: If drawing after every immediate mode triangle kills performance,
// change it to flush triangles whenever a drawing config register changes
// See: https://github.com/citra-emu/citra/pull/2866#issuecomment-327011550
VideoCore::g_renderer->Rasterizer()->DrawTriangles();
if (g_debug_context) {
g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch,
nullptr);
}
} }
} }
} }
@ -250,16 +259,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
} }
case PICA_REG_INDEX(pipeline.gpu_mode): case PICA_REG_INDEX(pipeline.gpu_mode):
if (regs.pipeline.gpu_mode == PipelineRegs::GPUMode::Configuring) { // This register likely just enables vertex processing and doesn't need any special handling
MICROPROFILE_SCOPE(GPU_Drawing);
// Draw immediate mode triangles when GPU Mode is set to GPUMode::Configuring
VideoCore::g_renderer->Rasterizer()->DrawTriangles();
if (g_debug_context) {
g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
}
}
break; break;
case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[0], 0x23c): case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[0], 0x23c):
@ -398,6 +398,11 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
range.second, range.first); range.second, range.first);
} }
VideoCore::g_renderer->Rasterizer()->DrawTriangles();
if (g_debug_context) {
g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
}
break; break;
} }
@ -632,6 +637,6 @@ void ProcessCommandList(const u32* list, u32 size) {
} }
} }
} // namespace } // namespace CommandProcessor
} // namespace } // namespace Pica