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arm_disasm: ARMv6 parallel add/sub media instructions
{S, U, Q, UQ, SH, UH}{ADD16, ASX, SAX, SUB16, ADD8, SUB8}
This commit is contained in:
aroulin
parent
0be8e1bfb6
commit
4a1db13072
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@ -69,18 +69,36 @@ static const char *opcode_names[] = {
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"orr",
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"pkh",
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"pld",
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"qadd16",
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"qadd8",
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"qasx",
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"qsax",
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"qsub16",
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"qsub8",
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"rev",
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"rev16",
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"revsh",
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"rsb",
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"rsc",
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"sadd16",
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"sadd8",
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"sasx",
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"sbc",
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"sel",
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"sev",
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"shadd16",
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"shadd8",
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"shasx",
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"shsax",
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"shsub16",
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"shsub8",
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"smlal",
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"smull",
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"ssat",
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"ssat16",
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"ssax",
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"ssub16",
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"ssub8",
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"stc",
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"stm",
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"str",
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@ -104,10 +122,28 @@ static const char *opcode_names[] = {
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"sxth",
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"teq",
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"tst",
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"uadd16",
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"uadd8",
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"uasx",
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"uhadd16",
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"uhadd8",
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"uhasx",
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"uhsax",
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"uhsub16",
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"uhsub8",
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"umlal",
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"umull",
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"uqadd16",
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"uqadd8",
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"uqasx",
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"uqsax",
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"uqsub16",
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"uqsub8",
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"usat",
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"usat16",
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"usax",
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"usub16",
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"usub8",
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"uxtab",
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"uxtab16",
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"uxtah",
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@ -262,6 +298,43 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassemblePKH(insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_QADD16:
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case OP_QADD8:
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case OP_QASX:
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case OP_QSAX:
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case OP_QSUB16:
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case OP_QSUB8:
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case OP_SADD16:
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case OP_SADD8:
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case OP_SASX:
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case OP_SHADD16:
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case OP_SHADD8:
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case OP_SHASX:
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case OP_SHSAX:
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case OP_SHSUB16:
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case OP_SHSUB8:
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case OP_SSAX:
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case OP_SSUB16:
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case OP_SSUB8:
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case OP_UADD16:
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case OP_UADD8:
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case OP_UASX:
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case OP_UHADD16:
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case OP_UHADD8:
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case OP_UHASX:
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case OP_UHSAX:
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case OP_UHSUB16:
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case OP_UHSUB8:
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case OP_UQADD16:
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case OP_UQADD8:
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case OP_UQASX:
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case OP_UQSAX:
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case OP_UQSUB16:
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case OP_UQSUB8:
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case OP_USAX:
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case OP_USUB16:
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case OP_USUB8:
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return DisassembleParallelAddSub(opcode, insn);
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case OP_REV:
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case OP_REV16:
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case OP_REVSH:
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@ -732,6 +805,16 @@ std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
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return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
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}
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std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
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rd, rn, rm);
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}
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std::string ARM_Disasm::DisassemblePKH(uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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@ -1083,6 +1166,49 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
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}
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}
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Opcode ARM_Disasm::DecodeParallelAddSub(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 21);
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uint32_t op2 = BITS(insn, 5, 7);
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uint32_t is_unsigned = BIT(insn, 22);
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if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
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return OP_UNDEFINED;
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// change op1 range from [1, 3] to range [0, 2]
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op1--;
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// change op2 range from [0, 4] U {7} to range [0, 5]
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if (op2 == 0x7)
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op2 = 0x5;
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static std::vector<Opcode> opcodes = {
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// op1 = 0
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OP_SADD16, OP_UADD16,
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OP_SASX, OP_UASX,
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OP_SSAX, OP_USAX,
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OP_SSUB16, OP_USUB16,
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OP_SADD8, OP_UADD8,
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OP_SSUB8, OP_USUB8,
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// op1 = 1
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OP_QADD16, OP_UQADD16,
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OP_QASX, OP_UQASX,
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OP_QSAX, OP_UQSAX,
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OP_QSUB16, OP_UQSUB16,
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OP_QADD8, OP_UQADD8,
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OP_QSUB8, OP_UQSUB8,
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// op1 = 2
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OP_SHADD16, OP_UHADD16,
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OP_SHASX, OP_UHASX,
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OP_SHSAX, OP_UHSAX,
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OP_SHSUB16, OP_UHSUB16,
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OP_SHADD8, OP_UHADD8,
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OP_SHSUB8, OP_UHSUB8
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};
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uint32_t opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
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return opcodes[opcode_index];
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}
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Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 22);
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uint32_t a = BITS(insn, 16, 19);
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@ -1220,6 +1346,9 @@ Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
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uint32_t rn = BITS(insn, 0, 3);
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switch (BITS(op1, 3, 4)) {
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case 0x0:
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// unsigned and signed parallel addition and subtraction
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return DecodeParallelAddSub(insn);
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case 0x1:
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// Packing, unpacking, saturation, and reversal
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return DecodePackingSaturationReversal(insn);
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@ -50,18 +50,36 @@ enum Opcode {
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OP_ORR,
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OP_PKH,
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OP_PLD,
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OP_QADD16,
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OP_QADD8,
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OP_QASX,
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OP_QSAX,
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OP_QSUB16,
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OP_QSUB8,
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OP_REV,
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OP_REV16,
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OP_REVSH,
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OP_RSB,
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OP_RSC,
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OP_SADD16,
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OP_SADD8,
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OP_SASX,
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OP_SBC,
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OP_SEL,
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OP_SEV,
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OP_SHADD16,
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OP_SHADD8,
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OP_SHASX,
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OP_SHSAX,
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OP_SHSUB16,
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OP_SHSUB8,
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OP_SMLAL,
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OP_SMULL,
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OP_SSAT,
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OP_SSAT16,
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OP_SSAX,
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OP_SSUB16,
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OP_SSUB8,
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OP_STC,
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OP_STM,
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OP_STR,
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@ -85,10 +103,28 @@ enum Opcode {
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OP_SXTH,
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OP_TEQ,
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OP_TST,
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OP_UADD16,
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OP_UADD8,
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OP_UASX,
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OP_UHADD16,
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OP_UHADD8,
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OP_UHASX,
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OP_UHSAX,
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OP_UHSUB16,
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OP_UHSUB8,
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OP_UMLAL,
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OP_UMULL,
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OP_UQADD16,
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OP_UQADD8,
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OP_UQASX,
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OP_UQSAX,
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OP_UQSUB16,
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OP_UQSUB8,
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OP_USAT,
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OP_USAT16,
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OP_USAX,
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OP_USUB16,
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OP_USUB8,
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OP_UXTAB,
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OP_UXTAB16,
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OP_UXTAH,
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@ -153,6 +189,7 @@ class ARM_Disasm {
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static Opcode Decode10(uint32_t insn);
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static Opcode Decode11(uint32_t insn);
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static Opcode DecodeSyncPrimitive(uint32_t insn);
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static Opcode DecodeParallelAddSub(uint32_t insn);
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static Opcode DecodePackingSaturationReversal(uint32_t insn);
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static Opcode DecodeMUL(uint32_t insn);
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static Opcode DecodeMSRImmAndHints(uint32_t insn);
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@ -175,6 +212,7 @@ class ARM_Disasm {
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static std::string DisassembleMRS(uint32_t insn);
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static std::string DisassembleMSR(uint32_t insn);
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassembleParallelAddSub(Opcode opcode, uint32_t insn);
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static std::string DisassemblePKH(uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassembleREV(Opcode opcode, uint32_t insn);
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