mirror of
https://gitlab.com/suyu-emu/suyu.git
synced 2024-03-15 23:15:44 +00:00
VideoCore: Fix channels with disk pipeline/shader cache.
This commit is contained in:
parent
d7990c159e
commit
3f8e7a5585
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@ -28,12 +28,11 @@ bool ComputePipelineKey::operator==(const ComputePipelineKey& rhs) const noexcep
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}
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ComputePipeline::ComputePipeline(const Device& device, TextureCache& texture_cache_,
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BufferCache& buffer_cache_, Tegra::MemoryManager& gpu_memory_,
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Tegra::Engines::KeplerCompute& kepler_compute_,
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ProgramManager& program_manager_, const Shader::Info& info_,
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std::string code, std::vector<u32> code_v)
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: texture_cache{texture_cache_}, buffer_cache{buffer_cache_}, gpu_memory{gpu_memory_},
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kepler_compute{kepler_compute_}, program_manager{program_manager_}, info{info_} {
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BufferCache& buffer_cache_, ProgramManager& program_manager_,
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const Shader::Info& info_, std::string code,
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std::vector<u32> code_v)
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: texture_cache{texture_cache_}, buffer_cache{buffer_cache_},
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program_manager{program_manager_}, info{info_} {
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switch (device.GetShaderBackend()) {
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case Settings::ShaderBackend::GLSL:
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source_program = CreateProgram(code, GL_COMPUTE_SHADER);
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@ -86,7 +85,7 @@ void ComputePipeline::Configure() {
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GLsizei texture_binding{};
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GLsizei image_binding{};
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const auto& qmd{kepler_compute.launch_description};
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const auto& qmd{kepler_compute->launch_description};
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const auto& cbufs{qmd.const_buffer_config};
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const bool via_header_index{qmd.linked_tsc != 0};
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const auto read_handle{[&](const auto& desc, u32 index) {
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@ -101,12 +100,12 @@ void ComputePipeline::Configure() {
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const u32 secondary_offset{desc.secondary_cbuf_offset + index_offset};
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const GPUVAddr separate_addr{cbufs[desc.secondary_cbuf_index].Address() +
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secondary_offset};
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const u32 lhs_raw{gpu_memory.Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory.Read<u32>(separate_addr)};
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const u32 lhs_raw{gpu_memory->Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory->Read<u32>(separate_addr)};
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return TexturePair(lhs_raw | rhs_raw, via_header_index);
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}
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}
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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return TexturePair(gpu_memory->Read<u32>(addr), via_header_index);
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}};
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const auto add_image{[&](const auto& desc, bool blacklist) {
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for (u32 index = 0; index < desc.count; ++index) {
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@ -49,10 +49,8 @@ static_assert(std::is_trivially_constructible_v<ComputePipelineKey>);
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class ComputePipeline {
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public:
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explicit ComputePipeline(const Device& device, TextureCache& texture_cache_,
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BufferCache& buffer_cache_, Tegra::MemoryManager& gpu_memory_,
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Tegra::Engines::KeplerCompute& kepler_compute_,
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ProgramManager& program_manager_, const Shader::Info& info_,
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std::string code, std::vector<u32> code_v);
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BufferCache& buffer_cache_, ProgramManager& program_manager_,
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const Shader::Info& info_, std::string code, std::vector<u32> code_v);
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void Configure();
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@ -60,11 +58,17 @@ public:
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return writes_global_memory;
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}
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void SetEngine(Tegra::Engines::KeplerCompute* kepler_compute_,
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Tegra::MemoryManager* gpu_memory_) {
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kepler_compute = kepler_compute_;
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gpu_memory = gpu_memory_;
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}
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private:
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TextureCache& texture_cache;
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BufferCache& buffer_cache;
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Tegra::MemoryManager& gpu_memory;
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Tegra::Engines::KeplerCompute& kepler_compute;
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Tegra::MemoryManager* gpu_memory;
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Tegra::Engines::KeplerCompute* kepler_compute;
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ProgramManager& program_manager;
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Shader::Info info;
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@ -169,15 +169,15 @@ ConfigureFuncPtr ConfigureFunc(const std::array<Shader::Info, 5>& infos, u32 ena
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}
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} // Anonymous namespace
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GraphicsPipeline::GraphicsPipeline(
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const Device& device, TextureCache& texture_cache_, BufferCache& buffer_cache_,
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Tegra::MemoryManager& gpu_memory_, Tegra::Engines::Maxwell3D& maxwell3d_,
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ProgramManager& program_manager_, StateTracker& state_tracker_, ShaderWorker* thread_worker,
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VideoCore::ShaderNotify* shader_notify, std::array<std::string, 5> sources,
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std::array<std::vector<u32>, 5> sources_spirv, const std::array<const Shader::Info*, 5>& infos,
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const GraphicsPipelineKey& key_)
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: texture_cache{texture_cache_}, buffer_cache{buffer_cache_},
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gpu_memory{gpu_memory_}, maxwell3d{maxwell3d_}, program_manager{program_manager_},
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GraphicsPipeline::GraphicsPipeline(const Device& device, TextureCache& texture_cache_,
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BufferCache& buffer_cache_, ProgramManager& program_manager_,
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StateTracker& state_tracker_, ShaderWorker* thread_worker,
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VideoCore::ShaderNotify* shader_notify,
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std::array<std::string, 5> sources,
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std::array<std::vector<u32>, 5> sources_spirv,
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const std::array<const Shader::Info*, 5>& infos,
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const GraphicsPipelineKey& key_)
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: texture_cache{texture_cache_}, buffer_cache{buffer_cache_}, program_manager{program_manager_},
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state_tracker{state_tracker_}, key{key_} {
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if (shader_notify) {
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shader_notify->MarkShaderBuilding();
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@ -285,7 +285,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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buffer_cache.runtime.SetBaseStorageBindings(base_storage_bindings);
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buffer_cache.runtime.SetEnableStorageBuffers(use_storage_buffers);
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const auto& regs{maxwell3d.regs};
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const auto& regs{maxwell3d->regs};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE {
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const Shader::Info& info{stage_infos[stage]};
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@ -299,7 +299,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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++ssbo_index;
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}
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}
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const auto& cbufs{maxwell3d.state.shader_stages[stage].const_buffers};
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const auto& cbufs{maxwell3d->state.shader_stages[stage].const_buffers};
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const auto read_handle{[&](const auto& desc, u32 index) {
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ASSERT(cbufs[desc.cbuf_index].enabled);
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const u32 index_offset{index << desc.size_shift};
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@ -312,13 +312,13 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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const u32 second_offset{desc.secondary_cbuf_offset + index_offset};
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const GPUVAddr separate_addr{cbufs[desc.secondary_cbuf_index].address +
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second_offset};
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const u32 lhs_raw{gpu_memory.Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory.Read<u32>(separate_addr)};
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const u32 lhs_raw{gpu_memory->Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory->Read<u32>(separate_addr)};
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const u32 raw{lhs_raw | rhs_raw};
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return TexturePair(raw, via_header_index);
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}
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}
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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return TexturePair(gpu_memory->Read<u32>(addr), via_header_index);
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}};
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const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
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for (u32 index = 0; index < desc.count; ++index) {
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@ -71,10 +71,9 @@ static_assert(std::is_trivially_constructible_v<GraphicsPipelineKey>);
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class GraphicsPipeline {
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public:
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explicit GraphicsPipeline(const Device& device, TextureCache& texture_cache_,
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BufferCache& buffer_cache_, Tegra::MemoryManager& gpu_memory_,
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Tegra::Engines::Maxwell3D& maxwell3d_,
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ProgramManager& program_manager_, StateTracker& state_tracker_,
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ShaderWorker* thread_worker, VideoCore::ShaderNotify* shader_notify,
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BufferCache& buffer_cache_, ProgramManager& program_manager_,
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StateTracker& state_tracker_, ShaderWorker* thread_worker,
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VideoCore::ShaderNotify* shader_notify,
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std::array<std::string, 5> sources,
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std::array<std::vector<u32>, 5> sources_spirv,
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const std::array<const Shader::Info*, 5>& infos,
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@ -107,6 +106,11 @@ public:
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};
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}
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void SetEngine(Tegra::Engines::Maxwell3D* maxwell3d_, Tegra::MemoryManager* gpu_memory_) {
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maxwell3d = maxwell3d_;
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gpu_memory = gpu_memory_;
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}
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private:
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template <typename Spec>
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void ConfigureImpl(bool is_indexed);
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@ -119,8 +123,8 @@ private:
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TextureCache& texture_cache;
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BufferCache& buffer_cache;
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Tegra::MemoryManager& gpu_memory;
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Tegra::Engines::Maxwell3D& maxwell3d;
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Tegra::MemoryManager* gpu_memory;
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Tegra::Engines::Maxwell3D* maxwell3d;
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ProgramManager& program_manager;
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StateTracker& state_tracker;
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const GraphicsPipelineKey key;
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@ -216,6 +216,7 @@ void RasterizerOpenGL::Draw(bool is_indexed, bool is_instanced) {
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return;
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}
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std::scoped_lock lock{buffer_cache.mutex, texture_cache.mutex};
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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SyncState();
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@ -477,9 +477,9 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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previous_program = &program;
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}
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auto* const thread_worker{build_in_parallel ? workers.get() : nullptr};
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return std::make_unique<GraphicsPipeline>(
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device, texture_cache, buffer_cache, *gpu_memory, *maxwell3d, program_manager,
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state_tracker, thread_worker, &shader_notify, sources, sources_spirv, infos, key);
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return std::make_unique<GraphicsPipeline>(device, texture_cache, buffer_cache, program_manager,
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state_tracker, thread_worker, &shader_notify, sources,
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sources_spirv, infos, key);
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} catch (Shader::Exception& exception) {
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LOG_ERROR(Render_OpenGL, "{}", exception.what());
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@ -533,9 +533,8 @@ std::unique_ptr<ComputePipeline> ShaderCache::CreateComputePipeline(
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break;
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}
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return std::make_unique<ComputePipeline>(device, texture_cache, buffer_cache, *gpu_memory,
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*kepler_compute, program_manager, program.info, code,
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code_spirv);
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return std::make_unique<ComputePipeline>(device, texture_cache, buffer_cache, program_manager,
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program.info, code, code_spirv);
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} catch (Shader::Exception& exception) {
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LOG_ERROR(Render_OpenGL, "{}", exception.what());
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return nullptr;
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@ -215,15 +215,14 @@ ConfigureFuncPtr ConfigureFunc(const std::array<vk::ShaderModule, NUM_STAGES>& m
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} // Anonymous namespace
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GraphicsPipeline::GraphicsPipeline(
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Tegra::Engines::Maxwell3D& maxwell3d_, Tegra::MemoryManager& gpu_memory_, Scheduler& scheduler_,
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BufferCache& buffer_cache_, TextureCache& texture_cache_,
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Scheduler& scheduler_, BufferCache& buffer_cache_, TextureCache& texture_cache_,
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VideoCore::ShaderNotify* shader_notify, const Device& device_, DescriptorPool& descriptor_pool,
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UpdateDescriptorQueue& update_descriptor_queue_, Common::ThreadWorker* worker_thread,
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PipelineStatistics* pipeline_statistics, RenderPassCache& render_pass_cache,
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const GraphicsPipelineCacheKey& key_, std::array<vk::ShaderModule, NUM_STAGES> stages,
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const std::array<const Shader::Info*, NUM_STAGES>& infos)
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: key{key_}, maxwell3d{maxwell3d_}, gpu_memory{gpu_memory_}, device{device_},
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texture_cache{texture_cache_}, buffer_cache{buffer_cache_}, scheduler{scheduler_},
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: key{key_}, device{device_}, texture_cache{texture_cache_},
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buffer_cache{buffer_cache_}, scheduler{scheduler_},
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} {
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if (shader_notify) {
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shader_notify->MarkShaderBuilding();
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@ -288,7 +287,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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buffer_cache.SetUniformBuffersState(enabled_uniform_buffer_masks, &uniform_buffer_sizes);
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const auto& regs{maxwell3d.regs};
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const auto& regs{maxwell3d->regs};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE {
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const Shader::Info& info{stage_infos[stage]};
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@ -302,7 +301,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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++ssbo_index;
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}
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}
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const auto& cbufs{maxwell3d.state.shader_stages[stage].const_buffers};
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const auto& cbufs{maxwell3d->state.shader_stages[stage].const_buffers};
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const auto read_handle{[&](const auto& desc, u32 index) {
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ASSERT(cbufs[desc.cbuf_index].enabled);
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const u32 index_offset{index << desc.size_shift};
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@ -315,13 +314,13 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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const u32 second_offset{desc.secondary_cbuf_offset + index_offset};
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const GPUVAddr separate_addr{cbufs[desc.secondary_cbuf_index].address +
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second_offset};
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const u32 lhs_raw{gpu_memory.Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory.Read<u32>(separate_addr)};
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const u32 lhs_raw{gpu_memory->Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory->Read<u32>(separate_addr)};
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const u32 raw{lhs_raw | rhs_raw};
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return TexturePair(raw, via_header_index);
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}
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}
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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return TexturePair(gpu_memory->Read<u32>(addr), via_header_index);
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}};
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const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
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for (u32 index = 0; index < desc.count; ++index) {
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@ -69,15 +69,16 @@ class GraphicsPipeline {
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static constexpr size_t NUM_STAGES = Tegra::Engines::Maxwell3D::Regs::MaxShaderStage;
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public:
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explicit GraphicsPipeline(
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Tegra::Engines::Maxwell3D& maxwell3d, Tegra::MemoryManager& gpu_memory,
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Scheduler& scheduler, BufferCache& buffer_cache, TextureCache& texture_cache,
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VideoCore::ShaderNotify* shader_notify, const Device& device,
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DescriptorPool& descriptor_pool, UpdateDescriptorQueue& update_descriptor_queue,
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Common::ThreadWorker* worker_thread, PipelineStatistics* pipeline_statistics,
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RenderPassCache& render_pass_cache, const GraphicsPipelineCacheKey& key,
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std::array<vk::ShaderModule, NUM_STAGES> stages,
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const std::array<const Shader::Info*, NUM_STAGES>& infos);
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explicit GraphicsPipeline(Scheduler& scheduler, BufferCache& buffer_cache,
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TextureCache& texture_cache, VideoCore::ShaderNotify* shader_notify,
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const Device& device, DescriptorPool& descriptor_pool,
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UpdateDescriptorQueue& update_descriptor_queue,
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Common::ThreadWorker* worker_thread,
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PipelineStatistics* pipeline_statistics,
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RenderPassCache& render_pass_cache,
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const GraphicsPipelineCacheKey& key,
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std::array<vk::ShaderModule, NUM_STAGES> stages,
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const std::array<const Shader::Info*, NUM_STAGES>& infos);
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GraphicsPipeline& operator=(GraphicsPipeline&&) noexcept = delete;
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GraphicsPipeline(GraphicsPipeline&&) noexcept = delete;
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@ -109,6 +110,11 @@ public:
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return [](GraphicsPipeline* pl, bool is_indexed) { pl->ConfigureImpl<Spec>(is_indexed); };
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}
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void SetEngine(Tegra::Engines::Maxwell3D* maxwell3d_, Tegra::MemoryManager* gpu_memory_) {
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maxwell3d = maxwell3d_;
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gpu_memory = gpu_memory_;
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}
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private:
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template <typename Spec>
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void ConfigureImpl(bool is_indexed);
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@ -120,8 +126,8 @@ private:
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void Validate();
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const GraphicsPipelineCacheKey key;
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Tegra::Engines::Maxwell3D& maxwell3d;
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Tegra::MemoryManager& gpu_memory;
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Tegra::Engines::Maxwell3D* maxwell3d;
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Tegra::MemoryManager* gpu_memory;
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const Device& device;
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TextureCache& texture_cache;
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BufferCache& buffer_cache;
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@ -555,10 +555,10 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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previous_stage = &program;
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}
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Common::ThreadWorker* const thread_worker{build_in_parallel ? &workers : nullptr};
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return std::make_unique<GraphicsPipeline>(
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*maxwell3d, *gpu_memory, scheduler, buffer_cache, texture_cache, &shader_notify, device,
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descriptor_pool, update_descriptor_queue, thread_worker, statistics, render_pass_cache, key,
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std::move(modules), infos);
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return std::make_unique<GraphicsPipeline>(scheduler, buffer_cache, texture_cache,
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&shader_notify, device, descriptor_pool,
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update_descriptor_queue, thread_worker, statistics,
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render_pass_cache, key, std::move(modules), infos);
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} catch (const Shader::Exception& exception) {
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LOG_ERROR(Render_Vulkan, "{}", exception.what());
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@ -190,6 +190,8 @@ void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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return;
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}
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std::scoped_lock lock{buffer_cache.mutex, texture_cache.mutex};
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// update engine as channel may be different.
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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BeginTransformFeedback();
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@ -885,12 +885,14 @@ void TextureCache<P>::InvalidateScale(Image& image) {
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}
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image.image_view_ids.clear();
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image.image_view_infos.clear();
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if constexpr (ENABLE_VALIDATION) {
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std::ranges::fill(state->graphics_image_view_ids, CORRUPT_ID);
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std::ranges::fill(state->compute_image_view_ids, CORRUPT_ID);
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for (auto& this_state : channel_storage) {
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if constexpr (ENABLE_VALIDATION) {
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std::ranges::fill(this_state.graphics_image_view_ids, CORRUPT_ID);
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std::ranges::fill(this_state.compute_image_view_ids, CORRUPT_ID);
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}
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this_state.graphics_image_table.Invalidate();
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this_state.compute_image_table.Invalidate();
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}
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state->graphics_image_table.Invalidate();
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state->compute_image_table.Invalidate();
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has_deleted_images = true;
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}
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