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Merge pull request #2042 from ReinUsesLisp/nouveau-tex
maxwell_3d: Allow texture handles with TIC id zero
This commit is contained in:
commit
10ab714fe0
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@ -35,8 +35,10 @@ void DmaPusher::DispatchCalls() {
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bool DmaPusher::Step() {
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if (dma_get != dma_put) {
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// Push buffer non-empty, read a word
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const CommandHeader command_header{
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Memory::Read32(*gpu.MemoryManager().GpuToCpuAddress(dma_get))};
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const auto address = gpu.MemoryManager().GpuToCpuAddress(dma_get);
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ASSERT_MSG(address, "Invalid GPU address");
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const CommandHeader command_header{Memory::Read32(*address)};
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dma_get += sizeof(u32);
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@ -42,8 +42,10 @@ void Fermi2D::HandleSurfaceCopy() {
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// TODO(Subv): Only raw copies are implemented.
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ASSERT(regs.operation == Regs::Operation::SrcCopy);
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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const auto source_cpu = memory_manager.GpuToCpuAddress(source);
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const auto dest_cpu = memory_manager.GpuToCpuAddress(dest);
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ASSERT_MSG(source_cpu, "Invalid source GPU address");
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ASSERT_MSG(dest_cpu, "Invalid destination GPU address");
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u32 src_bytes_per_pixel = RenderTargetBytesPerPixel(regs.src.format);
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u32 dst_bytes_per_pixel = RenderTargetBytesPerPixel(regs.dst.format);
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@ -52,22 +54,22 @@ void Fermi2D::HandleSurfaceCopy() {
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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Core::System::GetInstance().GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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rasterizer.FlushRegion(source_cpu, src_bytes_per_pixel * regs.src.width * regs.src.height);
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rasterizer.FlushRegion(*source_cpu, src_bytes_per_pixel * regs.src.width * regs.src.height);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu,
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rasterizer.InvalidateRegion(*dest_cpu,
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dst_bytes_per_pixel * regs.dst.width * regs.dst.height);
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if (regs.src.linear == regs.dst.linear) {
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// If the input layout and the output layout are the same, just perform a raw copy.
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ASSERT(regs.src.BlockHeight() == regs.dst.BlockHeight());
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Memory::CopyBlock(dest_cpu, source_cpu,
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Memory::CopyBlock(*dest_cpu, *source_cpu,
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src_bytes_per_pixel * regs.dst.width * regs.dst.height);
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return;
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}
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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u8* src_buffer = Memory::GetPointer(*source_cpu);
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u8* dst_buffer = Memory::GetPointer(*dest_cpu);
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if (!regs.src.linear && regs.dst.linear) {
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src.width, regs.src.height, regs.src.depth,
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@ -39,16 +39,17 @@ void KeplerMemory::ProcessData(u32 data) {
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ASSERT_MSG(regs.exec.linear, "Non-linear uploads are not supported");
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ASSERT(regs.dest.x == 0 && regs.dest.y == 0 && regs.dest.z == 0);
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GPUVAddr address = regs.dest.Address();
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VAddr dest_address =
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*memory_manager.GpuToCpuAddress(address + state.write_offset * sizeof(u32));
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const GPUVAddr address = regs.dest.Address();
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const auto dest_address =
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memory_manager.GpuToCpuAddress(address + state.write_offset * sizeof(u32));
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ASSERT_MSG(dest_address, "Invalid GPU address");
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// We have to invalidate the destination region to evict any outdated surfaces from the cache.
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// We do this before actually writing the new data because the destination address might contain
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// a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_address, sizeof(u32));
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rasterizer.InvalidateRegion(*dest_address, sizeof(u32));
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Memory::Write32(dest_address, data);
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Memory::Write32(*dest_address, data);
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Core::System::GetInstance().GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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state.write_offset++;
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@ -273,7 +273,8 @@ void Maxwell3D::ProcessQueryGet() {
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GPUVAddr sequence_address = regs.query.QueryAddress();
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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// VAddr before writing.
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std::optional<VAddr> address = memory_manager.GpuToCpuAddress(sequence_address);
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const auto address = memory_manager.GpuToCpuAddress(sequence_address);
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ASSERT_MSG(address, "Invalid GPU address");
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// TODO(Subv): Support the other query units.
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ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
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@ -386,14 +387,14 @@ void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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void Maxwell3D::ProcessCBData(u32 value) {
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// Write the input value to the current const buffer at the current position.
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GPUVAddr buffer_address = regs.const_buffer.BufferAddress();
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const GPUVAddr buffer_address = regs.const_buffer.BufferAddress();
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ASSERT(buffer_address != 0);
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// Don't allow writing past the end of the buffer.
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ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
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std::optional<VAddr> address =
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memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
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const auto address = memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
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ASSERT_MSG(address, "Invalid GPU address");
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Memory::Write32(*address, value);
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dirty_flags.OnMemoryWrite();
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@ -403,10 +404,11 @@ void Maxwell3D::ProcessCBData(u32 value) {
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}
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Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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const GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
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std::optional<VAddr> tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
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const GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
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const auto tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
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ASSERT_MSG(tic_address_cpu, "Invalid GPU address");
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(*tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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@ -415,10 +417,10 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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tic_entry.header_version == Texture::TICHeaderVersion::Pitch,
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"TIC versions other than BlockLinear or Pitch are unimplemented");
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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const auto r_type = tic_entry.r_type.Value();
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const auto g_type = tic_entry.g_type.Value();
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const auto b_type = tic_entry.b_type.Value();
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const auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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@ -427,10 +429,11 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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}
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Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
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GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
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const GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
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GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
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std::optional<VAddr> tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
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const GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
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const auto tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
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ASSERT_MSG(tsc_address_cpu, "Invalid GPU address");
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Texture::TSCEntry tsc_entry;
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Memory::ReadBlock(*tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
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@ -452,8 +455,10 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
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for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
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current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
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Texture::TextureHandle tex_handle{
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Memory::Read32(*memory_manager.GpuToCpuAddress(current_texture))};
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const auto address = memory_manager.GpuToCpuAddress(current_texture);
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ASSERT_MSG(address, "Invalid GPU address");
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const Texture::TextureHandle tex_handle{Memory::Read32(*address)};
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Texture::FullTextureInfo tex_info{};
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// TODO(Subv): Use the shader to determine which textures are actually accessed.
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@ -462,23 +467,16 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
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sizeof(Texture::TextureHandle);
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// Load the TIC data.
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if (tex_handle.tic_id != 0) {
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tex_info.enabled = true;
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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}
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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// Load the TSC data
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if (tex_handle.tsc_id != 0) {
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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}
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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if (tex_info.enabled)
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textures.push_back(tex_info);
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textures.push_back(tex_info);
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}
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return textures;
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@ -490,31 +488,28 @@ Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage,
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auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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GPUVAddr tex_info_address = tex_info_buffer.address + offset * sizeof(Texture::TextureHandle);
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const GPUVAddr tex_info_address =
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tex_info_buffer.address + offset * sizeof(Texture::TextureHandle);
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ASSERT(tex_info_address < tex_info_buffer.address + tex_info_buffer.size);
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std::optional<VAddr> tex_address_cpu = memory_manager.GpuToCpuAddress(tex_info_address);
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Texture::TextureHandle tex_handle{Memory::Read32(*tex_address_cpu)};
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const auto tex_address_cpu = memory_manager.GpuToCpuAddress(tex_info_address);
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ASSERT_MSG(tex_address_cpu, "Invalid GPU address");
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const Texture::TextureHandle tex_handle{Memory::Read32(*tex_address_cpu)};
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Texture::FullTextureInfo tex_info{};
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tex_info.index = static_cast<u32>(offset);
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// Load the TIC data.
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if (tex_handle.tic_id != 0) {
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tex_info.enabled = true;
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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}
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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// Load the TSC data
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if (tex_handle.tsc_id != 0) {
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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}
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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return tex_info;
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}
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@ -39,8 +39,10 @@ void MaxwellDMA::HandleCopy() {
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const GPUVAddr source = regs.src_address.Address();
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const GPUVAddr dest = regs.dst_address.Address();
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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const auto source_cpu = memory_manager.GpuToCpuAddress(source);
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const auto dest_cpu = memory_manager.GpuToCpuAddress(dest);
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ASSERT_MSG(source_cpu, "Invalid source GPU address");
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ASSERT_MSG(dest_cpu, "Invalid destination GPU address");
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// TODO(Subv): Perform more research and implement all features of this engine.
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ASSERT(regs.exec.enable_swizzle == 0);
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@ -64,7 +66,7 @@ void MaxwellDMA::HandleCopy() {
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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// y_count).
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if (!regs.exec.enable_2d) {
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Memory::CopyBlock(dest_cpu, source_cpu, regs.x_count);
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Memory::CopyBlock(*dest_cpu, *source_cpu, regs.x_count);
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return;
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}
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@ -73,8 +75,8 @@ void MaxwellDMA::HandleCopy() {
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// rectangle. There is no need to manually flush/invalidate the regions because
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// CopyBlock does that for us.
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for (u32 line = 0; line < regs.y_count; ++line) {
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const VAddr source_line = source_cpu + line * regs.src_pitch;
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const VAddr dest_line = dest_cpu + line * regs.dst_pitch;
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const VAddr source_line = *source_cpu + line * regs.src_pitch;
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const VAddr dest_line = *dest_cpu + line * regs.dst_pitch;
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Memory::CopyBlock(dest_line, source_line, regs.x_count);
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}
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return;
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@ -87,12 +89,12 @@ void MaxwellDMA::HandleCopy() {
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const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) {
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// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
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// copying.
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rasterizer.FlushRegion(source_cpu, src_size);
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rasterizer.FlushRegion(*source_cpu, src_size);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu, dst_size);
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rasterizer.InvalidateRegion(*dest_cpu, dst_size);
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};
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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@ -105,8 +107,8 @@ void MaxwellDMA::HandleCopy() {
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copy_size * src_bytes_per_pixel);
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Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
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regs.src_params.size_x, src_bytes_per_pixel, source_cpu, dest_cpu,
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regs.src_params.BlockHeight(), regs.src_params.pos_x,
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regs.src_params.size_x, src_bytes_per_pixel, *source_cpu,
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*dest_cpu, regs.src_params.BlockHeight(), regs.src_params.pos_x,
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regs.src_params.pos_y);
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} else {
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ASSERT(regs.dst_params.size_z == 1);
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@ -119,7 +121,7 @@ void MaxwellDMA::HandleCopy() {
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::SwizzleSubrect(regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x,
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src_bpp, dest_cpu, source_cpu, regs.dst_params.BlockHeight());
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src_bpp, *dest_cpu, *source_cpu, regs.dst_params.BlockHeight());
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}
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}
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@ -154,7 +154,8 @@ std::optional<VAddr> MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
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const VAddr base_addr{PageSlot(gpu_addr)};
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if (base_addr == static_cast<u64>(PageStatus::Allocated) ||
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base_addr == static_cast<u64>(PageStatus::Unmapped)) {
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base_addr == static_cast<u64>(PageStatus::Unmapped) ||
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base_addr == static_cast<u64>(PageStatus::Reserved)) {
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return {};
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}
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@ -19,7 +19,8 @@ OGLBufferCache::OGLBufferCache(RasterizerOpenGL& rasterizer, std::size_t size)
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GLintptr OGLBufferCache::UploadMemory(Tegra::GPUVAddr gpu_addr, std::size_t size,
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std::size_t alignment, bool cache) {
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auto& memory_manager = Core::System::GetInstance().GPU().MemoryManager();
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const std::optional<VAddr> cpu_addr{memory_manager.GpuToCpuAddress(gpu_addr)};
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const auto cpu_addr{memory_manager.GpuToCpuAddress(gpu_addr)};
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ASSERT_MSG(cpu_addr, "Invalid GPU address");
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// Cache management is a big overhead, so only cache entries with a given size.
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// TODO: Figure out which size is the best for given games.
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@ -46,7 +46,9 @@ GLintptr PrimitiveAssembler::MakeQuadIndexed(Tegra::GPUVAddr gpu_addr, std::size
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auto [dst_pointer, index_offset] = buffer_cache.ReserveMemory(map_size);
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auto& memory_manager = Core::System::GetInstance().GPU().MemoryManager();
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const std::optional<VAddr> cpu_addr{memory_manager.GpuToCpuAddress(gpu_addr)};
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const auto cpu_addr{memory_manager.GpuToCpuAddress(gpu_addr)};
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ASSERT_MSG(cpu_addr, "Invalid GPU address");
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const u8* source{Memory::GetPointer(*cpu_addr)};
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for (u32 primitive = 0; primitive < count / 4; ++primitive) {
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@ -1008,10 +1008,6 @@ void RasterizerOpenGL::SetupTextures(Maxwell::ShaderStage stage, const Shader& s
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auto& unit = state.texture_units[current_bindpoint];
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const auto texture = maxwell3d.GetStageTexture(entry.GetStage(), entry.GetOffset());
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if (!texture.enabled) {
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unit.texture = 0;
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continue;
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}
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texture_samplers[current_bindpoint].SyncWithConfig(texture.tsc);
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@ -23,8 +23,10 @@ using VideoCommon::Shader::ProgramCode;
|
|||
static VAddr GetShaderAddress(Maxwell::ShaderProgram program) {
|
||||
const auto& gpu = Core::System::GetInstance().GPU().Maxwell3D();
|
||||
const auto& shader_config = gpu.regs.shader_config[static_cast<std::size_t>(program)];
|
||||
return *gpu.memory_manager.GpuToCpuAddress(gpu.regs.code_address.CodeAddress() +
|
||||
shader_config.offset);
|
||||
const auto address = gpu.memory_manager.GpuToCpuAddress(gpu.regs.code_address.CodeAddress() +
|
||||
shader_config.offset);
|
||||
ASSERT_MSG(address, "Invalid GPU address");
|
||||
return *address;
|
||||
}
|
||||
|
||||
/// Gets the shader program code from memory for the specified address
|
||||
|
|
|
@ -317,7 +317,6 @@ struct FullTextureInfo {
|
|||
u32 index;
|
||||
TICEntry tic;
|
||||
TSCEntry tsc;
|
||||
bool enabled;
|
||||
};
|
||||
|
||||
/// Returns the number of bytes per pixel of the input texture format.
|
||||
|
|
Loading…
Reference in a new issue