2018-02-12 04:44:12 +00:00
|
|
|
// Copyright 2018 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
|
|
|
#pragma once
|
|
|
|
|
2018-09-04 11:54:50 +00:00
|
|
|
#include <array>
|
2019-06-07 16:56:30 +00:00
|
|
|
#include <atomic>
|
2019-12-30 12:03:20 +00:00
|
|
|
#include <condition_variable>
|
2019-06-07 16:56:30 +00:00
|
|
|
#include <list>
|
2018-02-12 04:44:12 +00:00
|
|
|
#include <memory>
|
2019-06-08 20:45:25 +00:00
|
|
|
#include <mutex>
|
2018-02-12 04:44:12 +00:00
|
|
|
#include "common/common_types.h"
|
2019-06-07 16:56:30 +00:00
|
|
|
#include "core/hle/service/nvdrv/nvdata.h"
|
2018-03-23 18:58:27 +00:00
|
|
|
#include "core/hle/service/nvflinger/buffer_queue.h"
|
2018-11-24 04:20:56 +00:00
|
|
|
#include "video_core/dma_pusher.h"
|
2018-02-12 04:44:12 +00:00
|
|
|
|
2019-02-19 01:58:32 +00:00
|
|
|
using CacheAddr = std::uintptr_t;
|
|
|
|
inline CacheAddr ToCacheAddr(const void* host_ptr) {
|
|
|
|
return reinterpret_cast<CacheAddr>(host_ptr);
|
|
|
|
}
|
|
|
|
|
2019-07-19 14:50:40 +00:00
|
|
|
inline u8* FromCacheAddr(CacheAddr cache_addr) {
|
|
|
|
return reinterpret_cast<u8*>(cache_addr);
|
|
|
|
}
|
|
|
|
|
2019-02-16 03:05:17 +00:00
|
|
|
namespace Core {
|
|
|
|
class System;
|
|
|
|
}
|
|
|
|
|
2018-08-03 16:55:58 +00:00
|
|
|
namespace VideoCore {
|
2019-01-08 04:32:02 +00:00
|
|
|
class RendererBase;
|
|
|
|
} // namespace VideoCore
|
2018-08-03 16:55:58 +00:00
|
|
|
|
2018-02-12 04:44:12 +00:00
|
|
|
namespace Tegra {
|
|
|
|
|
2018-03-24 04:45:24 +00:00
|
|
|
enum class RenderTargetFormat : u32 {
|
2018-03-25 21:57:53 +00:00
|
|
|
NONE = 0x0,
|
2018-06-06 02:07:40 +00:00
|
|
|
RGBA32_FLOAT = 0xC0,
|
2018-06-30 19:23:13 +00:00
|
|
|
RGBA32_UINT = 0xC2,
|
2018-08-13 04:34:20 +00:00
|
|
|
RGBA16_UNORM = 0xC6,
|
2018-08-13 04:04:52 +00:00
|
|
|
RGBA16_UINT = 0xC9,
|
2018-04-16 00:41:02 +00:00
|
|
|
RGBA16_FLOAT = 0xCA,
|
2018-07-23 23:10:00 +00:00
|
|
|
RG32_FLOAT = 0xCB,
|
2018-08-13 12:55:16 +00:00
|
|
|
RG32_UINT = 0xCD,
|
2019-09-21 23:40:46 +00:00
|
|
|
RGBX16_FLOAT = 0xCE,
|
2018-07-23 20:56:52 +00:00
|
|
|
BGRA8_UNORM = 0xCF,
|
2018-09-10 03:41:37 +00:00
|
|
|
BGRA8_SRGB = 0xD0,
|
2018-04-16 00:41:02 +00:00
|
|
|
RGB10_A2_UNORM = 0xD1,
|
2018-03-22 21:40:11 +00:00
|
|
|
RGBA8_UNORM = 0xD5,
|
2018-04-16 00:41:02 +00:00
|
|
|
RGBA8_SRGB = 0xD6,
|
2018-08-10 15:44:43 +00:00
|
|
|
RGBA8_SNORM = 0xD7,
|
2018-08-20 12:26:54 +00:00
|
|
|
RGBA8_UINT = 0xD9,
|
2018-07-26 00:01:29 +00:00
|
|
|
RG16_UNORM = 0xDA,
|
|
|
|
RG16_SNORM = 0xDB,
|
|
|
|
RG16_SINT = 0xDC,
|
|
|
|
RG16_UINT = 0xDD,
|
|
|
|
RG16_FLOAT = 0xDE,
|
2018-06-06 02:57:16 +00:00
|
|
|
R11G11B10_FLOAT = 0xE0,
|
2020-02-25 20:19:34 +00:00
|
|
|
R32_SINT = 0xE3,
|
2018-08-13 12:55:16 +00:00
|
|
|
R32_UINT = 0xE4,
|
2018-08-01 13:31:42 +00:00
|
|
|
R32_FLOAT = 0xE5,
|
2018-08-08 05:22:48 +00:00
|
|
|
B5G6R5_UNORM = 0xE8,
|
2018-09-15 15:48:02 +00:00
|
|
|
BGR5A1_UNORM = 0xE9,
|
2018-08-13 03:02:34 +00:00
|
|
|
RG8_UNORM = 0xEA,
|
2018-08-10 16:07:37 +00:00
|
|
|
RG8_SNORM = 0xEB,
|
2018-08-11 18:01:50 +00:00
|
|
|
R16_UNORM = 0xEE,
|
|
|
|
R16_SNORM = 0xEF,
|
|
|
|
R16_SINT = 0xF0,
|
|
|
|
R16_UINT = 0xF1,
|
2018-07-26 04:19:15 +00:00
|
|
|
R16_FLOAT = 0xF2,
|
2018-07-24 21:47:50 +00:00
|
|
|
R8_UNORM = 0xF3,
|
2018-08-12 01:44:42 +00:00
|
|
|
R8_UINT = 0xF6,
|
2018-03-22 21:40:11 +00:00
|
|
|
};
|
|
|
|
|
2018-07-02 17:42:04 +00:00
|
|
|
enum class DepthFormat : u32 {
|
|
|
|
Z32_FLOAT = 0xA,
|
|
|
|
Z16_UNORM = 0x13,
|
|
|
|
S8_Z24_UNORM = 0x14,
|
|
|
|
Z24_X8_UNORM = 0x15,
|
|
|
|
Z24_S8_UNORM = 0x16,
|
|
|
|
Z24_C8_UNORM = 0x18,
|
2018-07-25 01:41:40 +00:00
|
|
|
Z32_S8_X24_FLOAT = 0x19,
|
2018-07-02 17:42:04 +00:00
|
|
|
};
|
|
|
|
|
2018-04-25 02:57:10 +00:00
|
|
|
/// Returns the number of bytes per pixel of each rendertarget format.
|
|
|
|
u32 RenderTargetBytesPerPixel(RenderTargetFormat format);
|
|
|
|
|
2018-08-11 18:01:50 +00:00
|
|
|
/// Returns the number of bytes per pixel of each depth format.
|
|
|
|
u32 DepthFormatBytesPerPixel(DepthFormat format);
|
|
|
|
|
2018-09-06 13:48:08 +00:00
|
|
|
struct CommandListHeader;
|
2018-03-22 20:19:35 +00:00
|
|
|
class DebugContext;
|
|
|
|
|
2018-03-23 01:04:30 +00:00
|
|
|
/**
|
|
|
|
* Struct describing framebuffer configuration
|
|
|
|
*/
|
|
|
|
struct FramebufferConfig {
|
|
|
|
enum class PixelFormat : u32 {
|
|
|
|
ABGR8 = 1,
|
2019-08-21 05:22:54 +00:00
|
|
|
RGB565 = 4,
|
2019-01-11 20:15:30 +00:00
|
|
|
BGRA8 = 5,
|
2018-03-23 01:04:30 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
VAddr address;
|
|
|
|
u32 offset;
|
|
|
|
u32 width;
|
|
|
|
u32 height;
|
|
|
|
u32 stride;
|
|
|
|
PixelFormat pixel_format;
|
2018-03-23 18:58:27 +00:00
|
|
|
|
|
|
|
using TransformFlags = Service::NVFlinger::BufferQueue::BufferTransformFlags;
|
|
|
|
TransformFlags transform_flags;
|
2019-02-27 03:47:49 +00:00
|
|
|
Common::Rectangle<int> crop_rect;
|
2018-03-23 01:04:30 +00:00
|
|
|
};
|
|
|
|
|
2018-03-18 20:15:05 +00:00
|
|
|
namespace Engines {
|
|
|
|
class Fermi2D;
|
|
|
|
class Maxwell3D;
|
2018-06-10 22:02:33 +00:00
|
|
|
class MaxwellDMA;
|
2019-01-22 23:49:31 +00:00
|
|
|
class KeplerCompute;
|
2018-09-08 20:58:20 +00:00
|
|
|
class KeplerMemory;
|
2018-03-18 20:15:05 +00:00
|
|
|
} // namespace Engines
|
|
|
|
|
2018-02-12 04:44:12 +00:00
|
|
|
enum class EngineID {
|
|
|
|
FERMI_TWOD_A = 0x902D, // 2D Engine
|
|
|
|
MAXWELL_B = 0xB197, // 3D Engine
|
2019-01-22 23:49:31 +00:00
|
|
|
KEPLER_COMPUTE_B = 0xB1C0,
|
2018-02-12 04:44:12 +00:00
|
|
|
KEPLER_INLINE_TO_MEMORY_B = 0xA140,
|
|
|
|
MAXWELL_DMA_COPY_A = 0xB0B5,
|
|
|
|
};
|
|
|
|
|
2019-03-04 04:54:16 +00:00
|
|
|
class MemoryManager;
|
|
|
|
|
2019-02-09 04:21:53 +00:00
|
|
|
class GPU {
|
2018-02-12 04:44:12 +00:00
|
|
|
public:
|
2019-06-10 12:19:27 +00:00
|
|
|
explicit GPU(Core::System& system, VideoCore::RendererBase& renderer, bool is_async);
|
2019-01-08 04:32:02 +00:00
|
|
|
|
2019-03-07 20:57:08 +00:00
|
|
|
virtual ~GPU();
|
2018-02-12 04:44:12 +00:00
|
|
|
|
2018-11-24 04:20:56 +00:00
|
|
|
struct MethodCall {
|
|
|
|
u32 method{};
|
|
|
|
u32 argument{};
|
|
|
|
u32 subchannel{};
|
|
|
|
u32 method_count{};
|
|
|
|
|
|
|
|
bool IsLastCall() const {
|
|
|
|
return method_count <= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
MethodCall(u32 method, u32 argument, u32 subchannel = 0, u32 method_count = 0)
|
|
|
|
: method(method), argument(argument), subchannel(subchannel),
|
|
|
|
method_count(method_count) {}
|
|
|
|
};
|
|
|
|
|
|
|
|
/// Calls a GPU method.
|
|
|
|
void CallMethod(const MethodCall& method_call);
|
2018-02-12 04:44:12 +00:00
|
|
|
|
2019-07-26 18:20:43 +00:00
|
|
|
void FlushCommands();
|
|
|
|
|
2018-08-28 14:57:56 +00:00
|
|
|
/// Returns a reference to the Maxwell3D GPU engine.
|
|
|
|
Engines::Maxwell3D& Maxwell3D();
|
|
|
|
|
2018-07-20 22:31:36 +00:00
|
|
|
/// Returns a const reference to the Maxwell3D GPU engine.
|
|
|
|
const Engines::Maxwell3D& Maxwell3D() const;
|
|
|
|
|
2019-07-15 01:25:13 +00:00
|
|
|
/// Returns a reference to the KeplerCompute GPU engine.
|
|
|
|
Engines::KeplerCompute& KeplerCompute();
|
|
|
|
|
|
|
|
/// Returns a reference to the KeplerCompute GPU engine.
|
|
|
|
const Engines::KeplerCompute& KeplerCompute() const;
|
|
|
|
|
2018-08-28 14:57:56 +00:00
|
|
|
/// Returns a reference to the GPU memory manager.
|
|
|
|
Tegra::MemoryManager& MemoryManager();
|
2018-03-22 20:19:35 +00:00
|
|
|
|
2018-08-28 14:57:56 +00:00
|
|
|
/// Returns a const reference to the GPU memory manager.
|
|
|
|
const Tegra::MemoryManager& MemoryManager() const;
|
2018-02-12 04:44:12 +00:00
|
|
|
|
2018-11-24 04:20:56 +00:00
|
|
|
/// Returns a reference to the GPU DMA pusher.
|
|
|
|
Tegra::DmaPusher& DmaPusher();
|
|
|
|
|
2019-09-26 23:08:22 +00:00
|
|
|
// Waits for the GPU to finish working
|
|
|
|
virtual void WaitIdle() const = 0;
|
|
|
|
|
2019-09-25 23:43:23 +00:00
|
|
|
/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame.
|
2019-12-30 12:03:20 +00:00
|
|
|
void WaitFence(u32 syncpoint_id, u32 value);
|
2019-09-25 23:43:23 +00:00
|
|
|
|
2019-06-19 00:53:21 +00:00
|
|
|
void IncrementSyncPoint(u32 syncpoint_id);
|
2019-06-07 16:56:30 +00:00
|
|
|
|
2019-06-19 00:53:21 +00:00
|
|
|
u32 GetSyncpointValue(u32 syncpoint_id) const;
|
2019-06-07 16:56:30 +00:00
|
|
|
|
2019-06-19 00:53:21 +00:00
|
|
|
void RegisterSyncptInterrupt(u32 syncpoint_id, u32 value);
|
2019-06-08 01:13:20 +00:00
|
|
|
|
2019-06-19 00:53:21 +00:00
|
|
|
bool CancelSyncptInterrupt(u32 syncpoint_id, u32 value);
|
2019-06-07 16:56:30 +00:00
|
|
|
|
2020-02-10 14:32:51 +00:00
|
|
|
u64 GetTicks() const;
|
|
|
|
|
2019-06-19 00:53:21 +00:00
|
|
|
std::unique_lock<std::mutex> LockSync() {
|
|
|
|
return std::unique_lock{sync_mutex};
|
2019-06-08 02:13:40 +00:00
|
|
|
}
|
|
|
|
|
2019-06-10 12:19:27 +00:00
|
|
|
bool IsAsync() const {
|
|
|
|
return is_async;
|
|
|
|
}
|
|
|
|
|
2018-11-24 04:20:56 +00:00
|
|
|
/// Returns a const reference to the GPU DMA pusher.
|
|
|
|
const Tegra::DmaPusher& DmaPusher() const;
|
|
|
|
|
2019-01-30 02:49:18 +00:00
|
|
|
struct Regs {
|
|
|
|
static constexpr size_t NUM_REGS = 0x100;
|
|
|
|
|
|
|
|
union {
|
|
|
|
struct {
|
2019-11-03 23:54:03 +00:00
|
|
|
INSERT_UNION_PADDING_WORDS(0x4);
|
2019-01-30 02:49:18 +00:00
|
|
|
struct {
|
|
|
|
u32 address_high;
|
|
|
|
u32 address_low;
|
|
|
|
|
2019-03-27 16:12:53 +00:00
|
|
|
GPUVAddr SemaphoreAddress() const {
|
2019-01-30 02:49:18 +00:00
|
|
|
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
|
|
|
|
address_low);
|
|
|
|
}
|
2019-03-27 16:12:53 +00:00
|
|
|
} semaphore_address;
|
2019-01-30 02:49:18 +00:00
|
|
|
|
|
|
|
u32 semaphore_sequence;
|
|
|
|
u32 semaphore_trigger;
|
2019-11-03 23:54:03 +00:00
|
|
|
INSERT_UNION_PADDING_WORDS(0xC);
|
2019-01-30 02:49:18 +00:00
|
|
|
|
|
|
|
// The puser and the puller share the reference counter, the pusher only has read
|
|
|
|
// access
|
|
|
|
u32 reference_count;
|
2019-11-03 23:54:03 +00:00
|
|
|
INSERT_UNION_PADDING_WORDS(0x5);
|
2019-01-30 02:49:18 +00:00
|
|
|
|
|
|
|
u32 semaphore_acquire;
|
|
|
|
u32 semaphore_release;
|
2019-07-18 12:54:42 +00:00
|
|
|
u32 fence_value;
|
|
|
|
union {
|
|
|
|
BitField<4, 4, u32> operation;
|
|
|
|
BitField<8, 8, u32> id;
|
|
|
|
} fence_action;
|
2019-11-03 23:54:03 +00:00
|
|
|
INSERT_UNION_PADDING_WORDS(0xE2);
|
2019-01-30 02:49:18 +00:00
|
|
|
|
|
|
|
// Puller state
|
|
|
|
u32 acquire_mode;
|
|
|
|
u32 acquire_source;
|
|
|
|
u32 acquire_active;
|
|
|
|
u32 acquire_timeout;
|
|
|
|
u32 acquire_value;
|
|
|
|
};
|
|
|
|
std::array<u32, NUM_REGS> reg_array;
|
|
|
|
};
|
|
|
|
} regs{};
|
2019-01-24 03:17:55 +00:00
|
|
|
|
2019-04-09 18:02:00 +00:00
|
|
|
/// Performs any additional setup necessary in order to begin GPU emulation.
|
|
|
|
/// This can be used to launch any necessary threads and register any necessary
|
|
|
|
/// core timing events.
|
|
|
|
virtual void Start() = 0;
|
|
|
|
|
2019-01-21 20:18:09 +00:00
|
|
|
/// Push GPU command entries to be processed
|
2019-02-09 04:21:53 +00:00
|
|
|
virtual void PushGPUEntries(Tegra::CommandList&& entries) = 0;
|
2019-01-21 20:18:09 +00:00
|
|
|
|
|
|
|
/// Swap buffers (render frame)
|
2019-08-21 04:55:25 +00:00
|
|
|
virtual void SwapBuffers(const Tegra::FramebufferConfig* framebuffer) = 0;
|
2019-01-30 02:49:18 +00:00
|
|
|
|
2019-01-24 03:17:55 +00:00
|
|
|
/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
|
2019-02-19 01:58:32 +00:00
|
|
|
virtual void FlushRegion(CacheAddr addr, u64 size) = 0;
|
2019-01-24 03:17:55 +00:00
|
|
|
|
|
|
|
/// Notify rasterizer that any caches of the specified region should be invalidated
|
2019-02-19 01:58:32 +00:00
|
|
|
virtual void InvalidateRegion(CacheAddr addr, u64 size) = 0;
|
2019-01-24 03:17:55 +00:00
|
|
|
|
|
|
|
/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
|
2019-02-19 01:58:32 +00:00
|
|
|
virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
|
2019-01-24 03:17:55 +00:00
|
|
|
|
2019-06-07 16:56:30 +00:00
|
|
|
protected:
|
2019-06-19 00:53:21 +00:00
|
|
|
virtual void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const = 0;
|
2019-06-07 16:56:30 +00:00
|
|
|
|
2019-01-08 04:32:02 +00:00
|
|
|
private:
|
|
|
|
void ProcessBindMethod(const MethodCall& method_call);
|
|
|
|
void ProcessSemaphoreTriggerMethod();
|
|
|
|
void ProcessSemaphoreRelease();
|
|
|
|
void ProcessSemaphoreAcquire();
|
|
|
|
|
2019-01-21 20:18:09 +00:00
|
|
|
/// Calls a GPU puller method.
|
2019-01-08 04:32:02 +00:00
|
|
|
void CallPullerMethod(const MethodCall& method_call);
|
2019-01-24 03:17:55 +00:00
|
|
|
|
2019-01-21 20:18:09 +00:00
|
|
|
/// Calls a GPU engine method.
|
2019-01-08 04:32:02 +00:00
|
|
|
void CallEngineMethod(const MethodCall& method_call);
|
2019-01-24 03:17:55 +00:00
|
|
|
|
2019-01-21 20:18:09 +00:00
|
|
|
/// Determines where the method should be executed.
|
2019-01-08 04:32:02 +00:00
|
|
|
bool ExecuteMethodOnEngine(const MethodCall& method_call);
|
|
|
|
|
2019-02-09 04:21:53 +00:00
|
|
|
protected:
|
2018-11-24 04:20:56 +00:00
|
|
|
std::unique_ptr<Tegra::DmaPusher> dma_pusher;
|
2019-06-08 00:41:06 +00:00
|
|
|
Core::System& system;
|
2019-08-30 18:08:00 +00:00
|
|
|
VideoCore::RendererBase& renderer;
|
2018-08-28 14:57:56 +00:00
|
|
|
|
2019-02-09 04:21:53 +00:00
|
|
|
private:
|
|
|
|
std::unique_ptr<Tegra::MemoryManager> memory_manager;
|
|
|
|
|
2019-03-04 04:54:16 +00:00
|
|
|
/// Mapping of command subchannels to their bound engine ids
|
2018-09-04 11:54:50 +00:00
|
|
|
std::array<EngineID, 8> bound_engines = {};
|
2018-02-12 04:44:12 +00:00
|
|
|
/// 3D engine
|
|
|
|
std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
|
|
|
|
/// 2D engine
|
|
|
|
std::unique_ptr<Engines::Fermi2D> fermi_2d;
|
|
|
|
/// Compute engine
|
2019-01-22 23:49:31 +00:00
|
|
|
std::unique_ptr<Engines::KeplerCompute> kepler_compute;
|
2018-06-10 22:02:33 +00:00
|
|
|
/// DMA engine
|
|
|
|
std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
|
2018-09-08 20:58:20 +00:00
|
|
|
/// Inline memory engine
|
|
|
|
std::unique_ptr<Engines::KeplerMemory> kepler_memory;
|
2019-06-07 16:56:30 +00:00
|
|
|
|
|
|
|
std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
|
|
|
|
|
2019-06-12 11:52:49 +00:00
|
|
|
std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
|
2019-06-08 02:13:40 +00:00
|
|
|
|
2019-06-08 20:45:25 +00:00
|
|
|
std::mutex sync_mutex;
|
2019-06-10 12:19:27 +00:00
|
|
|
|
2019-12-30 12:03:20 +00:00
|
|
|
std::condition_variable sync_cv;
|
|
|
|
|
2019-06-10 12:19:27 +00:00
|
|
|
const bool is_async;
|
2018-02-12 04:44:12 +00:00
|
|
|
};
|
|
|
|
|
2019-01-30 02:49:18 +00:00
|
|
|
#define ASSERT_REG_POSITION(field_name, position) \
|
|
|
|
static_assert(offsetof(GPU::Regs, field_name) == position * 4, \
|
|
|
|
"Field " #field_name " has invalid position")
|
|
|
|
|
2019-03-27 16:12:53 +00:00
|
|
|
ASSERT_REG_POSITION(semaphore_address, 0x4);
|
2019-01-30 02:49:18 +00:00
|
|
|
ASSERT_REG_POSITION(semaphore_sequence, 0x6);
|
|
|
|
ASSERT_REG_POSITION(semaphore_trigger, 0x7);
|
|
|
|
ASSERT_REG_POSITION(reference_count, 0x14);
|
|
|
|
ASSERT_REG_POSITION(semaphore_acquire, 0x1A);
|
|
|
|
ASSERT_REG_POSITION(semaphore_release, 0x1B);
|
2019-07-18 12:54:42 +00:00
|
|
|
ASSERT_REG_POSITION(fence_value, 0x1C);
|
|
|
|
ASSERT_REG_POSITION(fence_action, 0x1D);
|
2019-01-30 02:49:18 +00:00
|
|
|
|
|
|
|
ASSERT_REG_POSITION(acquire_mode, 0x100);
|
|
|
|
ASSERT_REG_POSITION(acquire_source, 0x101);
|
|
|
|
ASSERT_REG_POSITION(acquire_active, 0x102);
|
|
|
|
ASSERT_REG_POSITION(acquire_timeout, 0x103);
|
|
|
|
ASSERT_REG_POSITION(acquire_value, 0x104);
|
|
|
|
|
|
|
|
#undef ASSERT_REG_POSITION
|
|
|
|
|
2018-02-12 04:44:12 +00:00
|
|
|
} // namespace Tegra
|